Theo Verelst Bwise Application Page

Growing collection of working (but under development) Bwise (Tcl/tk) applications and blocks. See also the latest Tcl/Tk Page! (24 Dec 1998)

Latest Drum track generator


Generates drumtracks from samples by graphical editing. This is a fairly random example of a drumtrack which includes a bass arpeggio based on samples generated by my physical modeling module.

Multiprocessor Simulation

I've called it this, because that's one of the things to do with it, but basically I've used the latest Bwise functionality to create a set of blocks with interconnection pattern, and provided a set of routines to deal with the connections and the possible signal progressions that result from a topology.

A few routines are added to the latest version of bwise are: wire_other wirename block_name pin_name
find the other end of a wire, and return a two element list containing the other end's block name and pin name.

pin_get_wirenames block_name pin_name
Returns al list with the names of all the wires connected to a pin.

block_get_pinnames block (pintype)
Return a list of the names of all the pins of a block, possibly limited to pintype type of pins. Currently pintype is used by new_block (see below) to distinguish between input and output blocks (resp. typein, typeout), but principally any legal tag assigned to pins can be used.

showactive block pin color
Mark a pin by changing its color, may be called with empty color argument

flood block pin
Start from a defined output pin, and graphically show the propagation of signals through the network, assuming that every pin and every wire that is in the forward path starts a sequence of resulting activity. In other words, the first pin spawns activity on each block that has an input connected by a wire to the chosen output, an in turn each of the outputs of these blocks is recursively treated the same, resulting in a 'flooding' of the network by activity. The activity is shown by pins ligting up in a different color, and has a pace of 1 seconds per set of all outputs of a block.
Note that this may not at all nbe a desirable way to compute and show possible iteractiosn in a network. The simplest addition would be to assume that at least all signals that flow between blocks that have multiple wires between them are processsed simulataneously. This is because the way things are handles recursively now, a long row of blocks generates a number of interactions that is power of the average number of them, so two connections per block, already grows as an exponential. More later on this, since it is not at all hard to impose any type of sequencing logic on the network elements, and also not to extract a list structure of an obvious one and process that list to fit certain demands.

netlistout (tag)
Return a list composed of 4-element sub-lists that contain pairs of block, pin definitions, representing the complete connectivity of a Bwise network. See below for an example, the idea is that no wire names are present in the output, and that the format is completely general. The sublist have output pins as the first value only, so each connection is accounted for only once, i.e. normally not forward and backward, as it could be in case of a bidirectional connection, which can be made by tagging pins as both input and output.

newblock name x y w h {pinsin} {pinsout} (tags)
The latest version of the parametrical block generator simply takes a rectangular shape wit pins on the left and right side to act as inputs and outputs. The list of pins can be of any length, and the whole block is automatically generated and placed in the bwise convas at the given position. Note the the name is an 'instance' or unique name, blocks with the same name are treated as one unit, which can be beneficial to define alternate block shapes, bysimply program the desired graphics and tagging then with the name of the block they belong to as the first tag.Even images can be made integral part of a block this way, and have pins attached to them that act as regular IO pins, and the resulting graphics can be moved around and connected up on the Bwise canvas just as any other block.
Take care that the heigth of the block is sufficient to accomodate the number of pins ((this may be automated in the future).

First, a simple example to represent the signal path in a basic analog-type of synthsizer, nota that only the units and signals are defined, not the functionality (at least not here).

It was created by generating the floowing blocks:

newblock EG1 100 100 70 40 {Trig} {Vout}
newblock EG2 100 100 70 40 {Trig} {Vout}
newblock KeyCV 100 100 70 40 {Range} {Vout Trig}
newblock VCF 100 100 70 40 {Vin Vc} {Vout}
newblock VCO 100 100 70 40 {Vin} {Vout}
newblock VCA 100 100 70 40 {Vin Vc} {Vout}

And dragging them into place. The following connect commands can be used to connect them up, or, alternatively the connections can be made by simply clicking on the two pins to turn them green, and press the Wire button:
connect wire13 VCO Vout VCF Vin 
connect wire14 VCA Vin VCF Vout 
connect wire21 VCO Vin KeyCV Vout 
connect wire24 VCA Vc EG2 Vout 
connect wire25 VCF Vc EG1 Vout 
connect wire26 EG2 Trig KeyCV Trig 
connect wire27 EG1 Trig KeyCV Trig 

Now for instance use flood KeyCV Trig, or flood KeyCV Vout, or issue them at the same time, by separating them by a semi colon. The activated pins will light up, and because there is no loop, after the last output has been activated, the sequence ends.

Use the netlistout command to obtain a block-oriented type of netlist:

% netlistout
 {VCO Vout VCF Vin} {VCF Vout VCA Vin} {EG1 Vout VCF Vc} 
  {EG2 Vout VCA Vc} {KeyCV Vout VCO Vin} {KeyCV Trig EG2 Trig} 
  {KeyCV Trig EG1 Trig}

Some more blocks To make sure some larger applications can also be graphically and netlist-wise represented without difficulty, I've made an array of processors (blocks) or 16 times 16 is 256:

The code to generate this was one (long) line:

set c 0; \
   for {set i 0} {$i < 16} {incr i} { 
   for {set j 0} {$j<16} {incr j} {
      incr c; \
      newblock FF$c [expr $j*60] [expr $i*60] 30 40 {in1 in2 } {out1 out2} {array l1};
      if {$c > 1} {
         connect wirea[expr $c] FF$c in1 FF[expr $c-1] out1; \
         connect wireb[expr $c] FF$c in2 FF[expr $c-1] out2; \
The blocks have been made somewhat small to accomodate all of them on the canves, a 8 times 8 fits a bit better.

Note that the graph above is not static at all. IT is not recommended to use the 'flood' algorithm on its connections, because 2 to the power of 256 is a very big number, and a tcl 'at' stack may not be enough to contain the amount of events, to put it mildly.

All interactive operations, such as selecting, deleting, adding wires and blocks fully operate on the graph. Graphically, tcl/tk performs more than fast enough on the pentium 100MHz machine I'm currently using, su picking up blocks and dragging them with the conneciton intact is easy.